1. Field of the Invention
The present invention relates to a signal generating circuit, and more particularly, to a phase lock loop (PLL) circuit applying MOS transistors with thicker gate oxide thicknesses as capacitor elements required within a filtering circuit (i.e., filter) to thereby improve an excessive leakage current caused by the whole PLL circuit while operating under a low supply voltage.
2. Description of the Prior Art
Owing to the development of semiconductor processes and the increasing availability of portable electronic apparatus, applying a low voltage design for diminishing a corresponding power and applying transistors having a smaller form factor has become a basic requirement of circuit design. The thicknesses of gate oxides of semiconductor elements are reduced as a result of the development of semiconductor processes from 0.18 micrometer semiconductors, to 0.13 micrometer semiconductors through to 65 nanometer semiconductors. Furthermore, for fitting the requirement of high speed and low power electronic circuit systems that are simultaneously capable of operating under a low voltage power supply system, most electronic circuit systems operate under a low supply voltage based on an all-digital process, wherein the all-digital process has the advantage of lower cost.
For modern circuit systems, a PLL (phase locked loop) circuit is a common electronic circuit used to generate clock signals by using a feedback scheme to reference instant phases of a reference signal and a feedback signal simultaneously, to thereby output a required stable clock signal. That is, when a phase relation between two different clock signals stays within a fixed range, the PLL circuit at this time is in a “phase locked” status.
In general, the operation of a PLL circuit (using a filtering circuit) is: converting a leading/lagging relation detected from a detecting circuit as a voltage/current signal to thereby control a frequency of an output oscillating signal (generated by a controllable oscillator) to achieve a goal of adjusting the phase of the output signal of the PLL circuit.
Please refer to FIG. 1; FIG. 1 is a block diagram of a prior art PLL circuit 100. As shown in FIG. 1, a PLL circuit 100 generally includes a detecting circuit 110 (such as a phase/frequency detector, PFD), a charge pump 120, a filtering circuit 130 (e.g., a loop filter), a controllable oscillator 140 (e.g., a voltage controlled oscillator, VCO), and a frequency divider 150. The detecting circuit 110 detects a phase relation between a reference signal CLKref and a feedback signal to thereby output a detecting signal, wherein the feedback signal here is a frequency-divided oscillating signal CLKdiv obtained by dividing a frequency of an oscillating signal CLKvco (as shown in FIG. 1) and the detecting signal is selectively an up signal UP or a down signal DN.
The charge pump 120 and the filtering circuit 130 then generates a control signal VCTR as an input signal of the controllable oscillator 140 according to the detecting signal (i.e., up signal UP or down signal DN); the controllable oscillator 140 hence is capable of adjusting the output signal (i.e., the oscillating signal CLKvco) according to the control signal VCTR. Since the above operation and concepts should be clear to persons skilled in the art, they are therefore not detailed herein.
For meeting modern requirements, in most cases the capacitor element of the filtering circuit within the PLL circuit will adopt the MOS (metal oxide semiconductor) capacitor of the advanced process, the said MOS capacitor having a thinner gate oxide thickness that therefore leads to excessive leakage current of the PLL circuit 100; moreover, the excessive leakage current makes the output clock of PLL circuit 100 have unwanted jitter or causes the operation of the PLL circuit 100 to fail.
Please refer to FIG. 2; FIG. 2 illustrates a waveform diagram of the control signal VCTR of the controllable oscillator 140. In advanced processes, the MOS capacitor with thin gate oxide thickness leads to excessive leakage current under normal operations, and the leakage current further causes the control signal VCTR to vary during a time interval between two individual operations of the detecting circuit 110, thereby affecting the output signal (oscillating signal CLKvco) of the said PLL circuit 100.
In addition, the said low supply voltage for advanced processes causes the charge pump 120 to have a bad performance, and makes the controllable oscillator 140 can only get a limited range of the input voltage. However, on the premise of a same required oscillating range, diminishing the range of input voltage of the controllable oscillator 140 will induce an increased gain of the controllable oscillator 140. That is, the bad linearity and small dynamical range of the charge pump 120 and unwanted huge gain of the controllable oscillator 140 will degrade the performance of the prior PLL circuit 100.
From these issues, it becomes clear there remains considerable room for improvement of PLL circuits.